1. Field of the Invention
The present invention relates to a solid-state imaging apparatus for use in a digital camera, a digital video camera, an endoscope, and the like.
Priority is claimed on Japanese Patent Application No. 2011-064248, filed on Mar. 23, 2011, the content of which is incorporated herein by this reference.
2. Description of Related Art
A time-to-digital converter (TDC) type analog-to-digital (A/D) converter is known as an A/D converter for measuring time (pulse width). FIG. 14 shows a configuration of the TDC type A/D converter of the related art. FIG. 15 shows an operation of the TDC type A/D converter of the related art. As shown in FIG. 14, the TDC type A/D converter is constituted by a delay circuit 102, a high-order counter circuit 103, a low-order latch circuit 104, and an encoder circuit 105.
The delay circuit 102 has a configuration in which a plurality of delay elements (one delay element 101a and seven delay elements 101b) such as INV and NAND circuits are arranged in a ring shape. Each delay element has a pulse input terminal to which a pulse is input and a pulse output terminal from which a pulse is output. The pulse input terminal is connected to a pulse output terminal of a previous-stage delay element. The pulse output terminal is connected to the pulse input terminal of a subsequent-stage delay element. The pulse output terminal of an eighth-stage delay element 101b is connected to the pulse input terminal of a first-stage delay element 101a, and eight delay elements are connected in a ring shape. These delay elements delay pulses input to pulse input terminals and output the delayed pulses from pulse output terminals. In addition, the first-stage delay element 101a has a second pulse input terminal to which a start pulse φStartP is input. The start pulse φStartP input to the first-stage delay element 101a is sequentially transmitted to a subsequent-stage delay element, so that a pulse signal is circulated within the delay circuit 102.
The high-order counter circuit 103 counts a pulse signal output by one delay element (the eighth delay element 101b of FIG. 14) constituting the delay circuit 102 as a count clock. The low-order latch circuit 104 retains (latches) an output signal of each delay element according to a sampling pulse φSamp. The encoder circuit 105 binarizes a value (phase data) retained in the low-order latch circuit 104.
Next, an operation of the TDC type A/D converter will be described using FIG. 15. Hereinafter, an example in which a pulse width of the sampling pulse φSamp is measured will be described. FIG. 15 shows waveforms of the sampling pulse φSamp and the start pulse φStartP, waveforms of output signals φCK1 to φCK8 of the delay elements constituting the delay circuit 102, and a signal φOCnt indicating a value counted by the high-order counter circuit 103. An output signal of an nth-stage delay element is denoted by φCKn.
First, the start pulse φStartP is switched from a low level to a high level at the same time at which the sampling pulse φSamp is switched from the low level to the high level (time T101). Thereby, the pulse signal is circulated within the delay circuit 102 as indicated by the output signals φCK1 to φCK8 of FIG. 15. After a predetermined period has elapsed from time T101, the low-order latch circuit 104 retains (latches) the output signal of the delay circuit 102 at the same time a count operation is ended at the timing (time T102) when the sampling pulse φSamp is switched from the high level to the low level.
At this time, a value (phase data) retained by the low-order latch circuit 104 corresponds to one of eight stages (states 0 to 7) as shown in FIG. 15. The encoder circuit 105 binarizes an output signal of the low-order latch circuit 104. An output signal of the encoder circuit 105 is output to a subsequent-stage circuit along with an output signal φOCnt of the high-order counter circuit 103. The output signal φOCnt of the high-order counter circuit 103 has a value corresponding to the number of circulations in which the start pulse φStartP has been circulated within the delay circuit 102, thereby configuring high-order data of digital data. In addition, the output signal of the encoder circuit 105 has a value corresponding to a running position of the start pulse φStartP within the delay circuit 102, thereby configuring low-order data of the digital data.
Thereby, it is possible to obtain digital data corresponding to a pulse width of the sampling pulse φSamp. At this time, since a value (8-bit data signal) retained by the low-order latch circuit 104 correspond tone of eight states, a 3-bit data signal is generated by binarizing a value.
There is a solid-state imaging apparatus (image sensor) as an application destination of the above-described A/D converter. In Japanese Unexamined Patent Application, First Publication No. 2009-33297, an example of an A/D converter arranged for each pixel column to A/D-convert an output from a pixel is described. An image sensor described in Japanese Unexamined Patent Application, First Publication No. 2009-33297 is an image sensor (of a single-slope type) that converts a pixel signal level (voltage information) into a pulse width (time information) and A/D-converts the pulse width by a TDC type A/D converter, thereby acquiring digital data corresponding to the pixel signal level. In addition, the image sensor described in Japanese Unexamined Patent Application, First Publication No. 2009-33297 retains phase data inside a column unit provided in correspondence with each pixel column and binarizes the phase data with an encoder circuit provided outside the column unit.